This invention relates to metal-oxide-semiconductor (MOS) transistors formed at the vertical sidewalls of trenches formed in layers of alternately doped semiconductor materials and, in particular, to construction using chemical vapor depositions and annealing to adjust the threshold voltage levels of those transistors.
Vertical MOS transistors, in general, have very narrow channel regions, those regions comprising thin layers between the source and drain layers. One method of decreasing the probability of undesired punch-through of the narrow channel regions at high bias voltages is to form the channel regions with impurity doping concentrations that are higher than the impurity doping concentrations in the source and drain areas. However, the high doping concentrations may result in transistors that, in many applications, have an undesirably high threshold voltage levels. Known prior-art vertical MOS transistor construction procedures and structures have not provided for adjustment of those high threshold voltage levels downward or, under other circumstances, for adjustment of the threshold voltage levels upward.